Priorty is claimed from Republic of Korean Patent Application No. 99-63900 filed Dec. 28, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device. More particularly, the present invention relates to a method of manufacturing a flash memory device capable of improving the operating characteristic of a flash memory device by increasing a coupling ratio of a gate electrode.
2. Description of the Prior Art
In a typical flash memory device, the contact area of a floating gate and a control gate is increased to increase a coupling ratio. In a stack gate flash memory device having a simplified stack structure, however, if its contact area is increased, as its cell size is accordingly increase, there is a limit to increasing the coupling ratio.
FIGS. 1 is a cross-sectional view of a conventional flash memory device.
As shown, after field oxide films 12 are formed on a semiconductor substrate 11 by well process, a tunnel oxide film 13 is formed. Then, a doped polysilicon layer is formed and is then patterned to form a floating gate 14. Next, after a dielectric film 15, a conductive layer for control gate 16 and an anti-reflection film 17 are sequentially formed on the entire structure, they are etched by self-alignment etching process, thus forming a stack gate structure of a floating gate 14 and a control gate 16.
FIGS. 2A and 2B are a schematic view showing capacitance generating between respective terminals of a flash memory device and an equivalent circuit diagram thereof.
If a drain voltage Vd is 0V, the floating gate voltage Vf can be expressed as the following Equation 1.
Vf=[(CiPo)/(CiPo+Cgs+Cgd+Cgb)]Vcgxe2x80x83xe2x80x83[Equation 1]
Where Cipo indicates a capacitance generated at the dielectric film, Cgs indicates a capacitance generated between a gate and a source. Cgd indicates a capacitance generated between gate and drain,. Cgb indicates a capacitance generated between a gate and bulk (or substrate) and Vcg indicates a control gate voltage.
If Vcg=0V, Vf can be expressed as the following Equation 2.
Vf=[(Vgd)/(CiPo+Cgs+Cgd+Cgb)]xe2x80x83xe2x80x83[Equation 2]
Then, as the resulting floating gate voltage Vf is the sum of Equation 1 and Equation 2 by a overlapping principle, the resulting floating gate voltage Vf can be expressed as the following Equation 3.
Vf={[(CiPo)/(CiPo+Cgs+Cgd+Cgb)]Vcg}+{[(Vgd)/(Cipo+Cgs+Cgd+Cgb)]Vd}xe2x80x83xe2x80x83[Equation 3]
From, Equation 3, it can be seen that if Cipo is increased, Vf is increased.
Therefore, the capacitance can be expressed into Equation 4.
xe2x80x83C=A(area)/L(length)xe2x80x83xe2x80x83[Equation 4]
As a result, if the contact area A of the floating gate and the control gate is increased. the floating gate voltage Vf can be increased. However, in a simplified stack-type cell structure, there is a limit to increasing the contact area of the floating gate and the control gate. Therefore, there occurs a problem that a device does not operate at a low voltage.
It is therefore an object of the present invention to provide a method of manufacturing a flash memory device in which a control gate is formed to surround a floating gate from its top to its bottom, in order to increase the contact area of the floating gate and the control gate, thereby increasing the coupling ratio of a gate electrode.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention is characterized in that it comprises the steps of growing a tunnel oxide film on a semiconductor substrate to which a device isolation process is performed; forming a nitride film and a first polysilicon layer for control gate on the tunnel oxide film; after removing the first polysilicon layer for a control gate. the nitride film and the tunnel oxide film on a portion of which a floating gate will be formed, forming a first dielectric film on the entire structure and then removing the first dielectric film on a portion of which the floating gate will be formed to expose the semiconductor substrate; forming a tunnel oxide film on the exposed semiconductor substrate and then forming a polysilicon layer for a floating gate on the entire structure; patterning the polysilicon layer for a floating gate, thus exposing the first polysilicon layer for a control gate located in the region other than the floating gate pattern; forming a second dielectric film on and at the sides of the patterned polysilicon layer for a floating gate; sequentially forming a second polysilicon layer for a control gate and an anti-reflection film on the entire structure; and patterning the control gate by self-alignment etching process to form a source region and a drain region.